There is a collaboration between Cadence Design Systems and Taiwan Semiconductor Manufacturing Company (TSMC) to develop 16nm FinFET technology specifically for mobile, networking, servers and FPGA usage. FinFETs are basically multi-gate devices which is distinguished by its thin silicon fin wrapped around the conducting channel, which allows the transistors to keep low level current leakage and faster switching performance.
Suk Lee, TSMC’s Senior Director for Design Infrastructure Marketing Division said,”The FinFET device requires greater accuracy, from analysis through signoff, and that is why TSMC is teaming with Cadence on this project. This collaboration will enable designers to use the new process technology with confidence earlier than ever before, allowing our mutual customers to meet their power, performance and time-to-market goals.”
The collaboration will help to have a required infrastructure to manufact
ure ultra low-power higher performance processors.